1. Field of the Invention
The present invention relates to data transmission networks and, in particular, to a method and apparatus for synchronization of cascaded multi-channel data transmissions between stations on a data transmission network by simultaneously initiating the retrieval of data from each transmission channel's elasticity buffer.
2. Discussion of the Prior Art
Communications between stations on a data transmission network occur through the transmission of a sequence, or "frame", of data characters. Adjacent frames are separated by characters that define an interframe gap and are distinguished from one another through the use of start and end delimiters. These delimiters may be either implicit or explicit. For example, a receiving station can implicitly establish the beginning and end of each frame by identifying transitions from no data characters to data characters and from data characters to no data characters, respectively. In other systems, the receiving station may rely on the use of a unique start code pattern and a unique stop code pattern to identify the exact beginning and the exact end of each frame.
When data frames are being transmitted through a sequence of stations in a network, it is necessary to compensate for timing difference between stations; these differences may arise because of frequency differences in the local clocks of the various stations on the network, physical variations in the transmission medium between stations and numerous other factors. If there is a timing difference between a transmitting station and a receiving station, then receiver data sampling for local use or repropagation of data characters on the network will drift, eventually causing data retrieval errors.
To accommodate these timing variations, each station in the network typically incorporates an elasticity buffer which causes received data characters to queue up before retransmission. The receiving station utilizes a clock recovered from the received data signal to write received data characters into its elasticity buffer and its own local read clock to sequentially retrieve the stored data characters from the elasticity buffer for retransmission in the order in which they were received.
An elasticity buffer is basically a cyclic buffer queue, that is, a series of sequentially accessed storage registers wherein access for a particular operation, i.e. write or read, returns or "wraps around" to the first register in the series after the last register in the series has been accessed for that operation. Write pointer logic, typically an incrementing counter, holds the address of the elasticity buffer storage register currently accessed for a write operation. Similarly, read pointer logic holds the address of the register currently accessed for a read operation.
In the case of a conventional elasticity buffer, the elasticity buffer's write pointer starts writing received data characters into the storage registers upon identification of an implicit or explicit start delimiter and stops advancing its write pointer after it has advanced beyond the storage register into which it has written the first character of the interframe gap. The elasticity buffer's read pointer starts reading data characters from the storage registers upon identification of a read-start signal and stops advancing, or "stalls", on the first character of the interframe gap. Thus, the reader "creates" as many additional interframe gap characters as it needs, regardless of the number that were received. Typically, the elasticity buffer stalls the read pointer upon identification of a frame preamble character. Then, when the next start delimiter is identified, the elasticity buffer begins sequentially reading storage registers from where it stalled.
Usually, the elasticity buffer circuitry that recognizes the start delimiter generates a "start detected" signal. After a delay and synchronization with the receiver's local byte clock, a "read-start" signal is in turn created that releases the read pointer to advance sequentially through the storage registers of the elasticity buffer. The delay allows data characters to accumulate in the elasticity buffer to ensure that even a station with the slowest allowable local clock that is receiving data from a transmitting station with the fastest allowable clock will not exhaust the elasticity buffer during receipt of the longest possible frame.
Some data transmission networks allow frames to be transmitted by the simultaneous cascaded transmission between stations of the multiple data characters comprising a frame via a plurality of transmission channels operating in tandem. Thus, in a network having N transmission channels between stations, a frame may be transmitted by placing the first data character in the frame sequence on the first channel, the second data character on the second channel and the Nth data character on the Nth channel, the initial data character on each channel being preceded by either an implicit or explicit start delimiter. Then, the N+1 data character is placed on the first channel, the N+2 data character is placed on the second channel and so on until all data characters in the frame are spread across the N channels.
There is no problem synchronizing the transmission of the multiple data characters over different channels, since the transmitting station's "local" clock can be used for timing each of the transmissions. However, as stated above, due to the different delays through the transmission media and the transmitter and receiver circuits, as well as frequency variations between the transmitting and receiving stations, synchronization problems for these cascaded, multi-channel serial transmissions can occur at the receiving station.
Thus, the receiving station must accurately reassemble all of the data characters that have been serially transmitted over the multiple channels utilizing the elasticity buffer associated with each channel and then simultaneously initiate retrieval of character-wide data from each channel's elasticity buffer in the exact sequence in which the data characters were received in order to accurately retransmit the frame.
To achieve this goal in a conventional multi-channel system, each channel is provided with an elasticity buffer to accomodate clock skew and synchronization followed by a separate first-in-first-out (FIFO) memory device to achieve alignment across the channels. Complex control logic in each channel starts copying data from its associated elasticity buffer when it detects a start delimiter. The host system begins reading the FIFOs when all FIFOs indicate that they are not empty. Additional throughput delay results because of the time required for the migration of the data through each FIFO.
It would, therefore, be highly desirable to have available a simple technique for cascading a number of receiver elasticity buffers while allowing simultaneous retrieval of character-wide data in the order that the data characters were received without utilizing external logic or lengthy FIFOs.